Dknute posted the following infos on his progress for his Dreamcast emulator Makaron:

The GD-EMU project has advanced a bit. Not without a fight though :)

Quartus SOPC Builder allows user to change component names to something more suitable than the default ones – so you can name JTAG UART anything you like but unless it’s “jtag_uart” there’s a very high chance it won’t work as NIOS IDE terminal.
There is a FAQ on that on Altera website, true, but it took me 2 days to find the information I was looking for…

I had some trouble figuring out a way to create a register stack that could be accessed for read/write operations from two separate interfaces – one synchronous (Avalon bus) and one asynchronous (GD ATA). It finally worked today, so now I can intercept ATA/ATAPI commands sent by Dreamcast on NIOS side, using C code.

33.8688MHz clock generator is finally complete. I’ve used 74AC04, though with short connections a HC part should do too. Output is clean enough for a clock, the only thing that worries me a bit is the voltage swing. Even if powered from 3.3V the generator manages to output a whooping 5Vp-p – probably due to parasitic capacitances that create a pump. I could put a small resistor in series with the output but that will form an unwanted low-pass RC filer… Looking at the specs the FPGA should be able to handle this kind of abuse. I hope.

Lastly I’ve wasted a better part of the day chasing bugs, before I realized I’m trying to control a memory-mapped I/O via cache. Not such a great idea :) Kinda funny seeing how just a few days ago I wrote a simple memory testing routine that bypasses the data cache, for the same purpose I/O accesses should.

I’ve already a pretty good idea of how the whole data exchange system should look like. On PC every operation could block the main emulation thread (if needed). That won’t work on the hardware – I need to deliver the data on time in every case. Including situations where audio playback has been started and a PIO/DMA request comes up as well.